Auto-enumeration of peripheral devices on a serial communication bus

ABSTRACT

Each device on a bus auto-enumerates at power up or reset to assign a unique address to the device based on the resistance value of an external resistor. A current source supplies a current to a terminal to which a resistor is coupled. Each device has a resistor attached with a different resistance value. Each device senses the voltage at the terminal and the voltage corresponds to the unique device address on the bus. Following enumeration, the devices on the bus are individually addressable using their unique address.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of provisional application 63/124,381filed Dec. 11, 2020, entitled “ENUMERATION OF PERIPHERAL DEVICES ON ASERIAL COMMUNICATION BUS”, naming as inventors James E. Heckroth et al.,which application is incorporated herein by reference.

This application is related to the application entitled “ENUMERATION OFPERIPHERAL DEVICES ON A SERIAL COMMUNICATION BUS” naming James E.Heckroth et al., as inventors, filed the same day as the presentapplication, application Ser. No. ______, attorney docket number176-0414, which application is incorporated herein by reference.

BACKGROUND Field of the Invention

This application relates to identification of devices on a serialcommunication bus.

Description of the Related Art

A host controller often needs to communicate with multiple peripheraldevices on a shared serial communications bus. In order to do this, somemethod of selecting, or “addressing” individual peripheral devices isrequired. One traditional approach is to provide an individual“chip-select” pin from the controller to each peripheral device. Thedownside of this approach is the number of pins required on the hostcontroller when there are a large number of peripheral devices to beaddressed.

FIG. 1 provides a block diagram illustrating a traditional serialcommunication arrangement using individual chip selects for eachperipheral device. The clock output signal from the controller 102 isrouted to the CLK input pins of all of the peripheral devices 104, 106,and 108 in parallel. The “Controller-Out, Peripheral-In” (COPI) serialdata output from the controller 102 is connected to all of theperipheral device “Shift Data In” (SDI) inputs in parallel. The “ShiftData Out” (SDO) serial data outputs from the peripheral devices areconnected together and routed to the “Controller-In, Peripheral-Out”(CIPO) serial data input of the controller. Individual active-low “ChipSelect” outputs from the host, labelled CS1_b through CSn_b, are routedto the active-low Chip Select input pin, CS_b, on each peripheraldevice, where the “b” indicates an active low signal. FIG. 1 alsoillustrates an example command structure 110 for a serial bus. Thecommand structure includes a Command followed by an address. The exampleshown in FIG. 1 shows a Read Register command followed by a registeraddress and a Write Register Command followed by a register address.

FIG. 2 depicts a single Write cycle, and a single Read Cycle, using thetraditional arrangement with individual peripheral device chip selects.In this case, the host controller asserts only one of the chip selectoutputs to select which peripheral device is being addressed. The“Command” issued by the host on the COPI output indicates whether thecycle is a “Write” or a “Read” and specifies the register address to bewritten to or read from, as depicted in FIG. 2. The “word length” usedfor commands and data are implementation-specific with common lengthsbeing 8 or 16 bits. The data transmission “DATA” follows the “CommandWord”. In the “Read” case, only the device addressed by the chip selectis allowed to output data on its SDO pin.

FIG. 3 depicts a sequence of multiple read cycles from multiple devicesusing the traditional arrangement with individual peripheral device chipselects. This sequence depicts three reads to each of three peripheraldevices to illustrate how successive reads to the same device can becascaded. Note that a read command issued to one peripheral devicecannot be followed immediately by a read command issued to a differentperipheral device, as the chip select must be asserted to the firstperipheral to allow the requested data to be returned. In theillustrated sequence, three read commands to the same device arefollowed by an unnamed command (“-”). The fourth unnamed command cannotbe a command (e.g. read or write command) that requires a subsequentdata transmission without adding another chip select cycle, but could beany “self-contained” command to the addressed device.

Another common approach is to use a “daisy-chaining” arrangement inwhich data from the host is shifted through multiple peripheral devicesin series using a common chip select signal. In this case, theperipheral device effectively takes on an address that is the device'sposition in the daisy-chain. This arrangement has the disadvantage ofhigh “clock-cycle overhead” required when addressing a single peripheralin isolation. FIG. 4 provides a block diagram illustrating a traditionalserial communication “daisy-chain” arrangement. The clock output signalfrom the controller 402 is routed from the controller CLK output pin tothe CLK input pins of all of the peripheral devices 404, 406, and 408 inparallel. A single chip select output from the host controller is routedfrom the controller CS_b pin to all of the peripheral device chip selectinputs in parallel. The COPI serial data output from the controller isconnected only to the SDI input of the first peripheral device 404 inthe chain. The SDO output of the first peripheral device 404 is thenconnected to the SDI input of the second peripheral device 406 in thechain, and this continues such that the SDO output from the second-lastperipheral is connected to the SDI input of the last peripheral device408 in the chain. The SDO output from the last peripheral device 408 inthe chain is returned to the CIPO input of the controller 402.

The input shift registers 410, 412, and 414 of the peripheral devicesare thus connected in series as depicted in FIG. 4, effectively creatingan extended shift register whose length is the serial communicationprotocol word length times the number of devices in the chain. Forexample, if a 16-bit word length is used with a daisy-chain of length ndevices, the effective shift register word length would be 16×n. Thecontroller sends commands to peripheral devices 1 through n by shiftingout the commands end-to-end as a continuous 16×n-bit stream, with thecommand intended for peripheral device n shifted out first. At the endof the 16×n-bit transfer, the shift registers of each device containsthe command intended for that device. In this way, addressing ofindividual devices is determined by their position in the chain.

FIG. 5 depicts the sequencing of three reads from each of theperipherals in a daisy-chain of length n=3 to illustrate the process.Three read commands, one for each peripheral, are shifted out from thecontroller COPI pin during the first activation 501 of CS_b. At the endof this period the internal shift registers of the peripheral devicesare loaded with the requested data to be returned to the controller.During the next CS_b cycle 503, the “x” register data is shifted out ofthe cascaded peripheral device SDO pins, returning to the controllerCIPO input. As the “x” register data is being shifted out of theconcatenated peripheral device shift registers, a new set of commands toread the “y” register in each peripheral device is being shifted in.During the next CS_b cycle 505, the “y” register data is shifted out ofthe cascaded peripheral device SDO pins, returning to the controllerCIPO input. As the “y” register data is being shifted out of theconcatenated peripheral device shift registers, a new set of commands isbeing shifted in to read the “z” register data in each peripheraldevice, which data is returned in the next CS_b cycle 507 as unnamedcommands “-” are shifted in. FIG. 6 depicts an isolated read of the “x”register in CS_b cycles 601 and 603 from the second peripheral device(device 2) located in a daisy-chain of n=3 devices. The “-” indicatesthe command/data on COPI and CIPO are commands data that are don'tcares. The example shown in FIG. 6 illustrates the clock-cycle penaltyassociated with the need to fill the shift registers of all devices inorder to access a single device.

It would be desirable to avoid the pin penalty associated with the largenumber of pins on the host controller when there are a large number ofperipheral devices to be addressed and the clock-cycle overhead presentin a daisy-chained approach.

SUMMARY OF EMBODIMENTS OF THE INVENTION

In one embodiment a peripheral device includes a terminal and a currentsource coupled to provide a current to the terminal. An address registerstores an address corresponding to a voltage on the terminal, theaddress to identify the peripheral device on a bus.

In another embodiment a system for auto-enumeration of devices on a busincludes a plurality of devices coupled to the bus. A first device ofthe plurality of devices including a first terminal, a first currentsource coupled to provide a first current to the first terminal, and afirst address register to store a first address corresponding to a firstvoltage on the first terminal. A second device of the plurality ofdevices includes a second terminal, a second current source coupled toprovide a second current to the second terminal, and a second addressregister to store a second address corresponding to a second voltage onthe second terminal.

In another embodiment a method for determining an address of a device ona bus includes supplying a terminal of the device with a current from acurrent source on the device. The device determines a voltage on theterminal and stores an address corresponding to the voltage in addressregister of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerousobjects, features, and advantages made apparent to those skilled in theart by referencing the accompanying drawings.

FIG. 1 illustrates traditional serial communication using individualperipheral chip selects.

FIG. 2 illustrates a single write cycle and a single read cycle usingindividual peripheral chip selects.

FIG. 3 illustrates multiple read cycles using individual peripheral chipselects.

FIG. 4 illustrates a traditional daisy-chain arrangement.

FIG. 5 illustrates multiple read cycles using daisy-chain arrangement

FIG. 6 illustrates a single read cycle using a daisy-chain arrangement.

FIG. 7 illustrates an embodiment of a serial communication arrangementwith enumerated peripheral devices.

FIG. 8 illustrates multiple read cycles using enumerated peripheraldevices.

FIG. 9 illustrates an embodiment of controller enumeration using adaisy-chain arrangement.

FIG. 10 illustrates an embodiment of peripheral device operation indaisy-chain mode with a switch position DC.

FIG. 11 illustrates an embodiment of peripheral device operation inparallel Mode with switch positions P, LP.

FIG. 12 illustrates an embodiment of enumeration with addressverification.

FIG. 13 illustrates an embodiment of an abbreviated enumeration commandwith automatic mode switching.

FIG. 14 illustrates an embodiment that uses a peripheral DC mode forswitch settings to implement a traditional multi-chip-select approach.

FIG. 15 illustrates a traction inverter in which the auto-enumerationdescribed herein is utilized.

FIG. 16 illustrates an embodiment for auto-enumeration using analogdetection.

FIG. 17 illustrates example voltage detection ranges forauto-enumeration.

FIG. 18 illustrates an example 6-level flash converter.

FIG. 19 illustrates a traction inverter in which the auto-enumerationdescribed herein is utilized.

The use of the same reference symbols in different drawings indicatessimilar or identical items.

DETAILED DESCRIPTION

If the peripheral devices can be “enumerated” with unique deviceaddresses, then host communications can be directed to individualperipheral devices by the inclusion of a “peripheral device address” inthe host-issued commands. That adds potential “overhead” in that thedevice address must be included in the host commands to the peripheraldevice, but that also allows communication with multiple peripheraldevices using a single chip select signal, and without requiringexcessive overhead when addressing individual devices in isolation.However, assigning “permanent” addresses for devices during devicemanufacturing is neither cost-effective nor practical. Embodimentsherein address how to efficiently and effectively enumerate theperipheral devices dynamically in the field while using a minimal numberof peripheral device pins and requiring no additional pins on the hostcontroller.

Several approaches for dynamic enumeration of unique peripheraladdresses are described herein. A first approach uses host controllerenumeration of serial-bus peripheral devices using a daisy-chainarrangement. The first approach requires only one additional pin on theperipheral device and requires no additional signaling or additionalpins on the host controller to accomplish enumeration.

FIG. 7 provides a block diagram of system 700 illustrating connection ofa serial bus controller 701 to multiple “enumerated” peripheral devices703, 705, and 707. In this case, each peripheral device 703, 705, 707has been enumerated with (i.e. assigned) a “unique” internal device“address” that is different than that of any other connected peripheraldevice. The controller CS_b, CLK, COPI, and CIPO lines are connected toall peripheral devices in parallel. The controller 701 addressesindividual peripheral devices by specifying a peripheral address in eachcommand sequence, thus eliminating the need for individual chip selectsignals for each peripheral. Another unique address, not assigned to anyof the individual peripheral devices, may be used as a “broadcast”peripheral device address. The host can write the same address in allperipheral devices by performing a write command to the broadcastaddress (broadcast read commands are not allowed, as multiple peripheraldevices cannot return data simultaneously). Each peripheral deviceresponds only to commands that specify an address that matches that ofthe device (or commands that specify the broadcast address, if used).

FIG. 7 also depicts an example “compact command structure” 709 whereinthe command word (e.g. Read command or Write command) embeds both thedevice address and the register address to be read from/written towithin the addressed device. If the device address and register addressdo not fit in the command word structure (e.g., due to a large numberenumerated devices, a large register set, and/or a smaller command wordsize), the same functions can be implemented using commands that arefollowed by subsequent data words.

FIG. 8 depicts three reads from three enumerated peripheral devices. Inthis case, the peripheral devices can be accessed by the controller inany order desired. During the first CS_b cycle 802, the command readdevice 1, register x is placed on the COPI signal line. During the CS_bcycle 804, the command read device 2, register x is placed on the COPIsignal line while at the same time device 1 register x data is placed onthe CIPO signal line. During the CS_b cycle 806, the command read device3, register x is placed on the COPI signal line, while device 2 registerx data is placed on the COPI signal line. During the CS_b cycle 808, thecommand read device 1, register y is placed on the COPI signal linewhile at the same time device 3 register x data is placed on the CIPOsignal line. Note that in the illustrated embodiment, during the CS-bcycle 808 the address in the command selects device 1 at the same timedevice 3 is putting data on the CIPO signal line. During the CS_b cycle810, the command read device 1, register z is placed on the COPI signalline while at the same time device 1 register y data is placed on theCIPO signal line. During the CS_b cycle 812, the command read device 2,register y is placed on the COPI signal line while at the same timedevice 1 register z data is placed on the CIPO signal line. During theCS_b cycle 814, the command read device 2, register z is placed on theCOPI signal line while at the same time device 2 register z data isplaced on the CIPO signal line. The reads continue reading variousregisters from various peripheral devices.

Peripheral device “enumeration”, i.e., the process of assigning uniqueaddresses to the peripheral devices, can be accomplished in a number ofdifferent ways. For example, the peripheral device address could be“permanently assigned” into on-chip read only memory (ROM) or one timeprogrammable (OTP) memory during the device production process. However,that approach presents a number of logistical problems (e.g. partserialization/marking, part tracking from device manufacturer to boardassembly) that render it impractical as compared to “dynamicallyassigned” methods. The peripheral device could include multiple logicinput pins used to specify the device address during operation. Thesepins would be pulled high or low by wiring and/or external components(e.g., pull-up and pull-down resistors, shift registers, memorycomponents) at the circuit board level. That approach has thedisadvantage of requiring multiple pins, with associated externalcircuitry and/or components, the number of which depend on the number ofperipherals that need to be addressed.

“Additional signaling” between the controller and each peripheral(signals other than the primary serial data output, serial data input,clock, and chip select) could be used as a “surrogate chip selects” toselect individual peripheral devices for enumeration. Enumeration canthen be coordinated by the host controller using a pre-defined protocolinvolving a combination of the primary serial communication signals andadditional signaling. The practicality of this approach depends on theavailability of such additional signaling in the application, and on theability of the host controller to implement the pre-defined enumerationprotocol using these additional signals.

New approaches for “dynamic” peripheral device enumeration are describedherein. These new approaches allow dynamic peripheral device enumerationwith a single chip select from the controller, and no additionalcontroller pins or signaling other than the primary serial communicationsignals (serial data output, serial data input, clock, and chip select).Both approaches described herein require only one pin on the peripheraldevice for enumeration. In the first approach the controller enumeratesthe peripheral serial-bus peripheral devices arranged in a daisy-chainusing only the standard serial communication bus signaling. The secondapproach described herein automatically enumerates serial-bus peripheraldevices using analog detection and requires no action on the part of thecontroller to accomplish the enumeration of peripheral devices.

FIG. 9 illustrates a system 900 and shows the connections between thecontroller 901 and the peripheral devices 903, 905, and 907 for a firstembodiment. In an embodiment system 900 is automotive traction inverterin which the controller 901 individually addresses six isolated gatedrivers as peripheral devices on a communication bus. The controller andthe peripheral devices utilize the traditional serial communicationpins, CS_b, CLK, SDI, and SDO, which were described earlier, as well asanother output pin, the “Shift Data In Through” (SDITHRU) pin. Thecontroller CS_b output is connected to the CS_b inputs of all peripheraldevices in parallel. The controller CLK output is connected to the CLKinputs of all peripheral devices in parallel. The controller COPI serialdata output is connected only to the SDI input of peripheral device 1(903). The SDITHRU output 909 from peripheral device 1 (903) isconnected to the SDI input of peripheral device 2 (905). The SDITHRUoutput 911 from peripheral device 2 (905) is connected to the SDI inputof peripheral 3, and this continues until the SDITHRU output of thesecond last peripheral device (Peripheral device n−1) is connected tothe SDI input of the last peripheral device in the sequence (Peripheraldevice n). Assuming three peripheral devices, the SDITHRU output 911 ofperipheral device 905 is connected to the SDI input of peripheral devicen (907). The SDO outputs from all peripheral devices are connectedtogether, along with the SDITHRU output 915 from peripheral device n(907), and returned to the controller 901 CIPO serial data input.

The peripheral devices have an internal switching mechanism 916, denoted“Switch” in FIG. 9, which configures the device to operate in one ofthree distinct modes: initial “Daisy-Chain” mode (switch position “DC”),post-enumeration a first parallel mode “Parallel” (switch position “P”),or a second parallel mode “Last Parallel” (switch position “LP”). Theswitch mechanism 916 configures the routing of the SDI input and the SDOand SDITHRU outputs as described herein.

In daisy-chain mode, the SDI input is routed only to the input of theinternal serial data shift register 917. The output of the shiftregister 917 is routed to the SDITHRU output, and the SDO output isdisabled and set to a high-impedance (Hi-Z) state as indicated by theSDO output being connected to the DC position, which is not connected.The daisy-chain mode allows the controller to address the peripheraldevices as a traditional daisy-chain arrangement, as depicted in FIG. 5.To the host controller 901, this configuration is the same as thetraditional daisy-chain arrangement of FIG. 4.

The peripheral devices default to the daisy-chain mode of operation atpower-on and after being reset, and daisy-chain mode is used duringinitial controller-initiated enumeration of the peripheral devices. Whenoperating in daisy-chain mode, peripheral devices will respond tocommands according to the address/command in the shift register 917 whenthe CS_b signal is deasserted. In an alternative implementation,daisy-chain mode peripheral devices respond only to a pre-determined“broadcast” address. In either case, in daisy-chain mode the hostcontroller addresses individual peripheral devices by nature of theirposition in the chain as described earlier. FIG. 9 also illustrates anexample command structure 930, which is described in more detail afteradditional enumeration and operational details are described.

FIG. 10 shows that in the daisy-chain mode of operation the SDI input isrouted only to the shift register 917 as indicated by the dotted line1001 between SDI and the P switch position. The dotted line 1003 betweenthe switch mechanism 916 and the SDO pin indicates the SDO pin is athigh impedance (Hi-Z). The dotted lines indicate no connection to the Pswitch positions in switch 916 in the daisy-chain mode of operation.

FIG. 11 illustrates the switch connections for parallel mode operation.The first parallel mode, shown as “P” in switch 916 is for the first N−1devices. In the first parallel mode, the SDI input is routed to theinput of the internal serial data shift register 917 and the output ofthe shift register is also routed to the SDO output. In the firstparallel mode, the SDI input is also routed “directly” to the SDITHRUoutput. The SDITHRU output is connected to the SDI input of theperipheral device that follows in the chain. For example, SDITHRU outputof peripheral device 1 (903) is connected to the SDI input of peripheraldevice 2 (905). That effectively connects the controller serial dataoutput (COPI) to the SDI inputs of all peripheral devices in parallel,provided that the accumulated propagation delays from SDI to SDITHRU donot result in violation of the setup and hold time requirements for SDIwith respect to CLK or CS_b.

In the second parallel (“Last Parallel”) mode, switch position LP, asshown for peripheral device n (907), the SDI input is routed only to theinput of the internal serial data shift register 917. The output of theshift register is routed to the SDO output, and the SDITHRU output isdisabled and set to a high-impedance (Hi-Z) state. The switch positionsand thus the connections for the various inputs and outputs arecontrolled according to whether the device is operating in thedaisy-chain mode of operation, the first parallel mode (P), or thesecond parallel mode (LP).

Post enumeration, peripheral devices 1 through n−1 are configured forthe first parallel mode of operation, while device n (the last device inthe chain) is configured for Last Parallel mode. That effectivelyresults in the arrangement depicted in FIG. 11. This post-enumerationparallel mode arrangement allows the controller to individually addressthe peripheral devices in the same way as the enumerated devicearrangement shown in FIG. 7.

The controller based enumeration requires that the controller “instruct”an addressed peripheral to enumerate (adopt the address provided by thecontroller), or to change operating mode (to DC, P or LP). In anembodiment these instructions are implemented using standard Writecommands to registers defined for enumeration purposes and for settingthe operating mode (DC, P, LP), or using designated “Enumerate” and “SetMode” commands defined for these purposes. In an embodiment the example“Compact Command Structure” 930 shown in FIGS. 9-11 assumes the use ofdedicated Enumerate and Set Mode commands. The Enumerate Commandincludes a Device Address to be assigned to the receiving peripheraldevice. The Set Mode command includes the mode (e.g., parallel mode (P)or last parallel mode(LP)) to which the peripheral device should switch.The Read Register and Write Register commands include the unique deviceaddress and the register address to which data is to be written or read.

The host controller initiates enumeration with the peripheral devicesoperating in daisy-chain mode as in FIG. 10. In daisy-chain mode thehost addresses individual peripheral devices by nature of their positionin the chain. The controller sends a unique Enumerate command (orcommand sequence) to each device in the chain. The Enumerate commandspecifies the unique device address to be assigned to that device. In anembodiment, the shift register is 8 bits long and the enumerate commandincludes, e.g., four bits to identify the command and 4 bits to identifythe unique address. Of course, longer shift registers can used, e.g., 16bits and/or a command sequence with a command followed by a data word isused in some embodiments. After enumeration has been completed, thecontroller sends the commands (or command sequences) to switch theoperating modes of the peripheral devices for post-enumeration paralleloperation. Once in parallel operation, the peripheral devices areaddressed as enumerated devices, each with a unique address as shown,e.g., in FIG. 7

An enumeration command sequence for a 3-device chain, including optionalread-back of the assigned addresses for verification prior to switchingto Post-enumeration Parallel operation, is illustrated in FIG. 12.During the first command sequence while CS-b is asserted at 1202 insingle bus operation, the controller transmits the initial enumerationcommands (e.g. “Enum Device 3 Address=011”) in traditional daisy-chainformat with each device receiving a unique address as part of theenumeration command the device receives.

In addition to the unique device addresses assigned to each peripheraldevice to allow individual device access, embodiments use a designated“broadcast” address to allow the controller to write to all peripheraldevices in parallel. Each peripheral device accepts write commandsaddressed to the devices own unique address, and write commandsaddressed to the broadcast address. Peripheral devices only respond toRead commands issued to their own unique addresses.

In the embodiment illustrated by FIG. 12, the peripheral devices storetheir assigned device address in a controller-readable register to allowoptional read-back verification of the enumeration. Followingenumeration, the controller issues a daisy-chain Read command sequence(e.g. “Read Device 3 Addr Reg”) during 1204 to read back the deviceaddress from each peripheral device to verify the enumeration. Thecontroller sends the command sequence instructing the peripheral devicesto change operating modes at 1206 as the peripheral devices return therequested enumeration data on CIPO. Note that the controller setsperipheral devices 1 through n−1 to Parallel (P) operating mode, whileperipheral device n is set to Last Parallel (LP) mode. Beginning withthe next chip select activation at 1208, the peripheral devices areconfigured in parallel mode, and are addressed by the controller asenumerated devices. The controller is then free to efficiently addressindividual peripheral devices in any sequence as illustrated at 1208,1210, 1212, and 1214. Note that the peripheral devices decode thecommands sent even if they are not addressed to know for example thatduring the CS-B assertion at 1214, the data on COPI follows a writecommand and should not be interpreted as a command. In addition, sincethe SDO terminals from the N−1 devices operating in parallel mode areconnected together along with the SDITHRU terminal of the lastperipheral device operating in last parallel mode, the peripheraldevices keep the SDO terminals (and SDITHRU for the last peripheraldevice) at high impedance unless a peripheral device receives a readcommand with its unique address, in which case the addressed peripheraldevice drives its SDO (or SDITHRU for the last peripheral) terminal withthe requested data.

In applications where the optional “read-back verification ofenumeration” is not required, the Enumeration and Set Mode commands canbe combined. In this case, the Enumerate command or command sequenceincludes both the device address and the post-enumeration operating modeto be assigned to the receiving peripheral device, and the mode would bechanged automatically at the end of the enumeration command cycle. FIG.13 illustrates enumeration of a 3-device chain using this abbreviatedenumeration command with automatic mode switching. In the bus operation1302 with chip select asserted, the combined enumeration commands aresent serially to the devices in the daisy-chain. During the busoperation 1304 and 1306 the controller sends read commands. The devicesrespond during 1306 and 1308 with the requested data. In bus operations1308 and 1310 the controller sends a write command with data.

Peripheral devices described in FIGS. 9-11, operating in daisy-chain(DC) mode can also be connected for use in traditional multi-chip-selectarrangements as illustrated in FIG. 14. The peripheral devices 1401,1403, 1405 default to operation in daisy-chain mode responsive to apower on or other reset condition, so no specific initialization isrequired for operation in the arrangement depicted in FIG. 14. Whenoperating in daisy-chain mode, peripheral devices will respond tocommands to any address. In an alternative implementation, daisy-chainmode peripheral devices respond only to a pre-determined “broadcast”address. In either case, when connected as illustrated in FIG. 14, thehost controller addresses individual peripheral devices using individualchip select signals as described in the discussion of FIG. 1.

FIG. 15 illustrates an exemplary embodiment for a traction inverter thatcontrols a three phase high voltage motor 1501. The controller 1502,which may be a microprocessor, microcontroller, or other suitableprocessing device, operates in a first domain (i.e., VDD1, e.g., 5 Volts(V)) and provides one or more control signals for a high-power loadsystem operating in a second domain (i.e., VDD3, e.g., 800 V). Thecontroller communicates with the peripheral devices, here gate drivers1504, 1506, 1508, 1510, 1512, and 1514 over communication bus 1515. Notethat the SDITHRU signal lines between gate drivers is also part of thecommunication bus 1515. The communication bus 1515 can be used by thecontroller to send, e.g., configuration information to the gate driversand receive status information from the gate drivers. Other controlsignals supplied by the controller to the gate drivers, e.g., pulse wavemodulated (PWM) signals to control the motor are omitted from FIG. 15for ease of illustration. Each of the gate drivers includes an isolationbarrier 1505 and an isolation communication channel (not separatelyshown) allowing control information to be communicated from the lowvoltage side of the gate driver to the high voltage side of the gatedriver. The communication bus 1515 is as described, e.g., in FIGS. 9-13,and includes a signal line to supply serial data in (SDI) of gate driver1504 from the COPI output of the controller 1502. The controller 1502further distributes the clock signal (CLK) and the chip select signal(CS_b) on the bus to the gate drivers in parallel. The SDITHRU outputfrom each gate driver is supplied to the SDI input of the next gatedriver in the chain. The SDO outputs of the gate drivers are connectedto each other and the CIPO input of the controller 1502. The SDITHRUoutput of the last gate driver in the chain 1514 is also connected toCIPO. The gate drivers supply gate control signals to the transistors1509 to control the motor 1501.

Another embodiment utilizes dynamic auto-enumeration of uniqueperipheral addresses and requires only one additional pin on eachperipheral device and requires no additional signaling or additionalpins on the host controller to accomplish enumeration. In an embodimentof the auto-enumeration approach, the additional peripheral device pinrequired for enumeration on the peripheral device is used only duringdevice initial configuration at power-on (or other reset condition), andis available for other use after configuration. In the auto-enumerationapproach, each peripheral device automatically enumerates based on thesensed value of an external resistor connected to a designated pin onthe device. The auto-enumeration approach requires no action from thehost controller.

FIG. 16 illustrates a system 1600 in which enumeration is based on asensed value of an external component such as a resistor. In anembodiment an external resistor is connected to the designatedenumeration pin (also referred to herein as terminal), ENUM, of eachperipheral device. A different external resistor value is used for eachperipheral device. The peripheral devices responds to a power oncondition, or to a device reset that occurs at power on or duringoperation, by automatically detecting a voltage on the EMUM pin that isdetermined by the value of the connected resistor and the device assignsits own peripheral device address according to a pre-determinedresistor-value-to-device-address mapping. The resistor-valueto-device-address mapping is determined by the voltage on the ENUM pin.Thus, to map the address based on the external resistor value, eachperipheral device 1603, 1605, 1607 provides a small bias current fromcurrent source 1610 to the ENUM pin, detects the voltage developed onthe external resistor 1612, and converts that voltage to a digital valueusing an analog-to-digital converter 1614. The digital value is used asthe basis for the device address on the bus, either directly or througha lookup table or other conversion mechanism from the digital value tothe address. The resistance value of each external resistor differs toidentify a different peripheral address. The current sources in thedevices provide nominally the same current so the difference in voltageis determined by the resistance value. Peripheral devices that includean analog-to-digital converter (ADC) for other purposes may use theexisting ADC for the enumeration process. If an ADC is not required forother reasons, embodiments use, e.g., a dedicated low-cost flashconverter for the detection process. The digital value of the voltage ismapped to an address as described further herein and stored in thedevice address register 1616. The physical pin used for the enumerationprocess may be re-used for other purposes after the enumeration has beencompleted.

The resolution required for the ADC used for resistor detection dependson the number of peripheral device addresses that must be resolved, theADC input voltage range (semiconductor process utilized forimplementation), the bias current level and current generator tolerance,and the tolerance of the external resistors.

In an embodiment, an automotive traction inverter application requiresthat a controller be able to individually address six isolated gatedrivers as peripheral devices on a Serial Peripheral Interface (SPI)serial communication bus. The peripheral devices include an on-chip ADCwith a full-scale input voltage range of 2.4V, and a 20 μA currentsource to bias the external enumeration resistors. In an embodiment theADC input voltage range is divided into 6 equal ranges for addressassignment as depicted in FIG. 17. Selecting resistor values of 10 kΩ,30 kΩ, 50 kΩ, 70 kΩ, 90 kΩ, and 110 kΩ for enumeration would positionthe resulting “nominal” V=I×R voltages in the center of the assignedranges. If the current generator tolerance is +/−5% and the externalresistors have 1% tolerance, the resulting voltages would have aworst-case range of +/−6% as illustrated in FIG. 17. Note that theresulting voltage variance increases linearly with the nominal resistorvalue, resulting in less margin for the higher voltage address “bins”.In this example, an 8-bit ADC with 2.4V full-scale input range wouldhave an LSB value of ˜9.4 mV which is more than adequate to resolve theresulting voltages with the illustrated margins without ambiguity. Ifadditional margin was desired or required, the address enumerationvoltage ranges can be spaced in a non-linear fashion to distribute themargin evenly.

After the enumeration is completed, the physical pin used forenumeration is available to be used for another function, provided thatthe other function is not required during power on initialization orreset. Ideally, the alternate use of the pin would be an output from theperipheral device, connected to high-impedance inputs on other devicesthat would not interfere with detection of the external resistor valueduring enumeration.

If a suitable ADC is not included for other purposes in the peripheraldevice, embodiments include a simple, low-cost flash converter 1800 forthe auto-enumeration function. For a system requiring the enumeration of6 SPI peripheral devices, an example 6-level flash converter design isillustrated in FIG. 18. The internal reference voltagesV_(SETi)=I_(REF)(i·R), i=0 . . . 6 are generated with 6 equal resistorsR 1802 and an internal reference current, I_(REF) 1804 such that thevoltages developed on each resistor are constant over temperature andprocess. Each of the six peripheral devices uses an external resistorR_(EXTi) 1806 and the internal bias current I_(BIAS) from current source1808 to generate the appropriate voltage on the ENUM pin V_(ENUM),according to the equation:

${V_{ENUMi} = {{I_{BIAS}R_{EXTi}} = \frac{V_{{SET}{({i - 1})}} + V_{{SET}{(i)}}}{2}}},{i = {1\mspace{14mu}\ldots\mspace{14mu} 6}}$

The six comparators COMPO through COMPS and the digital decoder 1810that follows the comparators generate a unique address for eachperipheral device. The determination of ENUM voltage is shown at 1812.Random inaccuracies in R_(EXTi), I_(REF), the 6 internal resistors 1802and random offset in the comparators lead to inaccuracies in eachV_(ENUMi) (V_(ENUMi)±Δ_(i)) and V_(SETi). These inaccuracies can betolerated with enough voltage separation between the 6 internalsetpoints.

Peripherals capable of sensing a voltage on an external resistor forenumeration can also be used in traditional “individual chip-select”arrangements by assigning the same address (e.g. same external resistorvalue) to each peripheral device.

FIG. 19 illustrates an embodiment for a traction inverter that controlsa three phase high voltage motor 1901 and the enumeration is performedusing the auto-enumeration approach described in relation to FIGS. 16-18using resistors R1 to R6. FIG. 19 illustrates an exemplary embodimentfor a traction inverter that controls a three phase high voltage motor1901. The controller 1902, which may be a microprocessor,microcontroller, or other suitable processing device, operates in afirst domain (i.e., VDD1, e.g., 5 Volts (V)) and provides one or morecontrol signals for a high-power load system operating in a seconddomain (i.e., VDD3, e.g., 800 V). The controller communicates with theperipheral devices, here gate drivers 1904, 1906, 1908, 1910, 1912, and1914 over communication bus 1915. Other control signals supplied by thecontroller to the gate drivers, e.g., pulse wave modulated (PWM) signalsto control the motor are omitted from FIG. 19 for ease of illustration.Each of the gate drivers includes an isolation barrier 1905 and anisolation communication channel (not separately shown) allowing controlinformation to be communicated from the low voltage side of the gatedriver to the high voltage side of the gate driver. The communicationbus 1915 is described, e.g., in FIG. 7, and includes a signal line tosupply serial data in (SDI) on all the gate drivers in parallel from theCOPI output of the controller 1902. The controller 1902 furtherdistributes the clock signal (CLK) and the chip select signal (CS_b) onthe bus to the gate drivers in parallel. The SDO outputs of the gatedrivers are connected to each other and the CIPO input of the controller1902. The gate drivers supply gate control signals to the transistors1909 to control the motor 1901.

Thus, approaches for enumeration of devices on a communication bus hasbeen described. The description of the invention set forth herein isillustrative and is not intended to limit the scope of the invention asset forth in the following claims. Variations and modifications of theembodiments disclosed herein, may be made based on the description setforth herein, without departing from the scope of the invention as setforth in the following claims.

What is claimed is:
 1. A peripheral device comprising: a terminal; acurrent source coupled to provide a current to the terminal; and anaddress register to store an address corresponding to a voltage on theterminal, the address to identify the peripheral device on a bus.
 2. Theperipheral device as recited in claim 1 further comprising an analog todigital converter to convert the voltage on the terminal to a digitalvalue indicative of the address.
 3. The peripheral device as recited inclaim 1 wherein the peripheral device responds to a command on the buscontaining the address in an address field of the command in accordancewith the command.
 4. The peripheral device as recited in claim 1 whereinthe address is stored in the address register responsive to a power oncondition.
 5. The peripheral device as recited in claim 1 wherein theaddress is stored in the address register responsive to reset.
 6. Theperipheral device as recited in claim 1 wherein the terminal is used asan output terminal during operation of the peripheral device after theaddress is determined.
 7. The peripheral device as recited in claim 1wherein the voltage is determined according to the current provided tothe terminal and a resistance coupled to the terminal.
 8. The peripheraldevice as recited in claim 1 further comprising a communicationinterface coupled to the bus, the communication interface including, aclock terminal, a serial data in terminal, a serial data out terminal,and a chip select terminal.
 9. A system for auto-enumeration of deviceson a bus comprising: a plurality of devices coupled to the bus; a firstdevice of the plurality of devices including a first terminal, a firstcurrent source coupled to provide a first current to the first terminal,and a first address register to store a first address corresponding to afirst voltage on the first terminal; and a second device of theplurality of devices including a second terminal, a second currentsource coupled to provide a second current to the second terminal, and asecond address register to store a second address corresponding to asecond voltage on the second terminal.
 10. The communication system asrecited in claim 9 further comprising a plurality of resistors coupledrespectively to the plurality of devices, a first resistor of theplurality of resistors is coupled to the first terminal and a secondterminal of the plurality of resistors is coupled to the secondterminal.
 11. The communication system as recited in claim 10 whereinthe first device is responsive to a command on the bus containing thefirst address and the second device is responsive to a second command onthe bus containing the second address.
 12. The communication system asrecited in claim 10 wherein the plurality of devices includes sixdevices including the first device and the second device, and each ofrespective voltages on respective terminals of the plurality of deviceshave a different voltage and nominal values of the respective voltagesare linearly spaced.
 13. The communication system as recited in claim 10wherein the plurality of devices includes six devices including thefirst device and the second device, and each of respective voltages onrespective terminals of the plurality of devices have a differentvoltage and wherein nominal values of the respective voltages arenon-linearly spaced.
 14. The communication system as recited in claim 9wherein the first device and the second device store the first addressand the second address, respectively, in the first address register andthe second address register responsive to a power on condition.
 15. Thecommunication system as recited in claim 9 wherein the first device andthe second device store the first address and the second address,respectively, in the first address register and the second addressregister responsive to a reset.
 16. The communication system as recitedin claim 9 wherein the first terminal is used as an output terminalfollowing determination of the first address.
 17. The communicationsystem as recited in claim 9 wherein each of the plurality of peripheraldevices comprises a communication interface coupled to the bus and thecommunication interface includes a clock terminal, a serial data interminal, a serial data out terminal, and a chip select terminal.
 18. Amethod for determining an address of a device on a bus comprising:supplying a terminal of the device with a current from a current sourceon the device; determining a voltage on the terminal; and storing anaddress corresponding to the voltage in address register of the device.19. The method as recited in claim 18 further comprising converting thevoltage to a digital value in an analog to digital converter.
 20. Themethod as recited in claim 18 further comprising the device respondingto a command on the bus containing the address in an address field ofthe command.
 21. The method as recited in claim 18 further comprisingstoring the address in the address register responsive to a power oncondition.
 22. The method as recited in claim 18 further comprisingstoring the address in the address register responsive to reset.
 23. Themethod as recited in claim 18 further comprising using the terminal asan output terminal during operation of the peripheral device after apower on condition.
 24. The method as recited in claim 18 furthercomprising generating the voltage according to the current and aresistance of a resistor coupled to the terminal.